The present invention relates to the structure of memory cells of a semiconductor memory device, and in particular a dynamic-random access memory (DRAM).
An example of a configuration of and a method of making a DRAM in the prior art is shown, Inoue, et al, "A Spread Stacked Capacitor (SSC) Cell for 64 Mbit DRAMs", International Electron Device Meeting (IEDM), pp. 31-34, Dec. 3-6, 1989. According to this prior art technology, parts of storage electrodes adjacent to each other are superimposed with each other to enlarge the capacitor area. As a result, it is possible to obtain DRAMs having a memory cell capacitance larger than an ordinary stacked capacitor cell.
To facilitate understanding of the present invention, the configuration of the DRAM, and a method of making it, shown in the above-mentioned literature will next be described with reference to FIG. 8A to FIG. 8F. FIG. 8A to FIG. 8E are diagrams showing the steps of fabrication of a DRAM in the prior art. FIG. 8F is a plan view of FIG. 8E.
First, a device isolating oxide film 12 is formed on a silicon substrate 10. Next, a gate oxide film 14 is formed on the silicon substrate 10 between the device isolation oxide films 12. Next, word lines 16 and data lines (not shown) are formed. Next, a first oxide film 18, a nitride film 20 and a second oxide film 22 are formed in turn over the entire surface of the silicon substrate 10, with the gate oxide film 14 and the like having been formed. Next, a first contact hole 24 extending through the first oxide film 18, the nitride film 20 and the second oxide film 22 is formed. Next, a first storage electrode 26 is formed by photolithography and etching on the second oxide film 22, filling the first contact hole 24 (FIG. 8A).
Next, a third oxide film 28 is formed over the entire surface of the laminate body including the first storage electrode 26 having been formed. Next, a second contact hole 30 extending through the first to third oxide films 18, 22 and 28, and the nitride film 20 is formed (FIG. 8B). The second contact hole 30 is used as a contact hole for a storage electrode adjacent to the first storage electrode 26.
Then, a second storage electrode 32 is formed on the third oxide film 28, filling the second contact hole 30, by means of photolithography and etching (FIG. 8C).
Then, the second and third oxide films 22 and 28 above the nitride film 20 are removed (FIG. 8D).
Next, a capacitor dielectric film 34 is formed to cover the surface of the first and second storage electrodes 26 and 32. Next, a cell plate 36 is formed on the capacitor dielectric film 34, so that the cell plate 36 is opposite to the first and second storage electrodes 26 and 32, through the capacitor dielectric film 34 (FIG. BE). The plan view of FIG. 8E is shown in FIG. 8F. FIG. 8E shows a section along line A--A in FIG. 8F.
In the conventional DRAM, parts of the first and second storage electrodes adjacent in the data line direction are superimposed with or overlap each other, and increase of the capacitance by the amount of overlap is intended.
The operation of the conventional semiconductor memory device will next be described. In each memory cell, the word line extends over the gate oxide film between the data line contact hole and the storage electrode contact hole, and the word line over the gate oxide film serves as the gate electrode for the switching device. The signal from the data line is given as an electric charge to the storage electrode via the storage electrode contact hole when the gate electrode is in the ON state. The storage electrode and the cell plate confronting the storage electrode via the capacitor dielectric film form a capacitive part. Normally, a constant voltage is applied to the cell plate, so that potential (electric charge) can be held as a bit signal in the capacitive part.
In the memory configuration obtained in the prior art example, the storage electrodes overlap only in the region up to the contact hole of the memory cells adjacent to each other. As a result, the prior art memory configuration is associated with a limitation to the increase in the area of the capacitor, and this imposes a limitation to further increase in the degree of integration. That is, it is difficult to maintain or enlarge the area of the storage electrode while reducing the area required for each memory cell.
In the steps of fabrication in the above described prior art example, the outer contour of the storage electrodes is defined, for each storage electrode, by photography and etching. As a result, the fabrication is complicated.